Conventional flash memory devices degrade over time as the device is programmed/erased and read. Vendors of flash memory devices publish data sheets listing a recommended worse case Error Correction Code (ECC) rate for each flash memory device that guarantees data integrity over a guaranteed program/erase cycle. However, at the beginning of the life cycle of a flash device, the flash device is not subject to as many bit errors, and does not need the correction power recommended by the flash vendors. Over the lifetime of a flash memory device, the flash memory device degrades and needs a lower ECC rate.
It would be desirable to implement a statistical adaptive error correction system for a flash memory device